High pass FIR filter design and implementation using FPGA

Dissertant

Sahar, Asad Hamid

Thesis advisor

Jasim, Manal Hammadi

University

University of Technology

Faculty

-

Department

Department of Electrical Engineering

University Country

Iraq

Degree

Master

Degree Date

2012

English Abstract

Digital filters can be classified into Finite Impulse Response (FIR) filters & Infinite Impulse Response (IIR) filters.

Depending on the response of the system, FIR Filters can be designed using frequency sampling or windowing methods; but These methods have a problem in precise control of the critical frequencies.

In the optimal method ( equiripple method), the weighted approximation error between the actual frequency response and the desired filter response is spread across the pass-band and the stop-band and the maximum error is minimized, resulting a ripples in the pass-band and the stop-band.

The optimal method (equiripple method) has the same tolerance requirements as the windowing method.

There is more than one way to implement the digital FIR filter.

Based on the design specification, careful choice of implementation method and tools can save a lot of time and work.

MATLAB is an excellent tool to design filters.

There are toolboxes available to generate VHDL descriptions of the filters which reduce dramatically the time required to generate a solution.

Time can be spent evaluating different implementation alternatives.

Field-Programmable Gate Array (FPGA) became an extremely cost-effective means of off-loading computationally intensive digital signal processing algorithms to improve overall system performance.

The FIR filter implementation in FPGA utilizing the dedicated hardware resources can effectively achieve Application-Specific Integrated Circuit (ASIC)-like performance, while reducing development time cost and risks.

In this work a digital FIR high pass filter using MATLAB program (FDATools) using equiripple and Kaiser window methods, then the design in the FPGA kit is downloaded by generating VHDL description.

A comparison the amount of the component has been used in the FPGA for both methods.

The FIR filter is implemented using Spartan 3AN- xc3s700a-4fg484 FPGA and simulated with the help of Xilinx ISE (Integrated Software Environment) Software WEBPACK project navigator 11i.

Main Subjects

Electronic engineering

• APA
• MLA
• AMA

Language

English

Data Type

Arab Theses

Record ID

BIM-418788