An Impulse-C Hardware Accelerator for Packet Classification Based on FineCoarse Grain Optimization
Joint Authors
Collier, R.
Grewal, G.
Areibi, Shawki
Ahmed, O.
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2013, Issue 2013 (31 Dec. 2013), pp.1-23, 23 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2013-10-24
Country of Publication
Egypt
No. of Pages
23
Main Subjects
Information Technology and Computer Science
Abstract EN
Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components.
The Packet Classification with Incremental Update (PCIU) algorithm, Ahmed et al.
(2010), is a novel and efficient packet classification algorithm with a unique incremental update capability that demonstrated excellent results and was shown to be scalable for many different tasks and clients.
While a pure software implementation can generate powerful results on a server machine, an embedded solution may be more desirable for some applications and clients.
Embedded, specialized hardware accelerator based solutions are typically much more efficient in speed, cost, and size than solutions that are implemented on general-purpose processor systems.
This paper seeks to explore the design space of translating the PCIU algorithm into hardware by utilizing several optimization techniques, ranging from fine grain to coarse grain and parallel coarse grain approaches.
The paper presents a detailed implementation of a hardware accelerator of the PCIU based on an Electronic System Level (ESL) approach.
Results obtained indicate that the hardware accelerator achieves on average 27x speedup over a state-of-the-art Xeon processor.
American Psychological Association (APA)
Ahmed, O.& Areibi, Shawki& Collier, R.& Grewal, G.. 2013. An Impulse-C Hardware Accelerator for Packet Classification Based on FineCoarse Grain Optimization. International Journal of Reconfigurable Computing،Vol. 2013, no. 2013, pp.1-23.
https://search.emarefa.net/detail/BIM-448123
Modern Language Association (MLA)
Ahmed, O.…[et al.]. An Impulse-C Hardware Accelerator for Packet Classification Based on FineCoarse Grain Optimization. International Journal of Reconfigurable Computing No. 2013 (2013), pp.1-23.
https://search.emarefa.net/detail/BIM-448123
American Medical Association (AMA)
Ahmed, O.& Areibi, Shawki& Collier, R.& Grewal, G.. An Impulse-C Hardware Accelerator for Packet Classification Based on FineCoarse Grain Optimization. International Journal of Reconfigurable Computing. 2013. Vol. 2013, no. 2013, pp.1-23.
https://search.emarefa.net/detail/BIM-448123
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-448123