A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors
Joint Authors
Kumar, Rakesh
Chen, Deming
Papakonstantinou, Alexandros
Akram, Shoaib
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2010, Issue 2010 (31 Dec. 2010), pp.1-22, 22 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2010-07-25
Country of Publication
Egypt
No. of Pages
22
Main Subjects
Information Technology and Computer Science
Abstract EN
Interconnection networks for multicore processors are traditionally designed to serve a diversity of workloads.
However, different workloads or even different execution phases of the same workload may benefit from different interconnect configurations.
In this paper, we first motivate the need for workload-adaptive interconnection networks.
Subsequently, we describe an interconnection network framework based on reconfigurable switches for use in medium-scale (up to 32 cores) shared memory multicore processors.
Our cost-effective reconfigurable interconnection network is implemented on a traditional shared bus interconnect with snoopy-based coherence, and it enables improved multicore performance.
The proposed interconnect architecture distributes the cores of the processor into clusters with reconfigurable logic between clusters to support workload-adaptive policies for inter-cluster communication.
Our interconnection scheme is complemented by interconnect-aware scheduling and additional interconnect optimizations which help boost the performance of multiprogramming and multithreaded workloads.
We provide experimental results that show that the overall throughput of multiprogramming workloads (consisting of two and four programs) can be improved by up to 60% with our configurable bus architecture.
Similar gains can be achieved also for multithreaded applications as shown by further experiments.
Finally, we present the performance sensitivity of the proposed interconnect architecture on shared memory bandwidth availability.
American Psychological Association (APA)
Akram, Shoaib& Papakonstantinou, Alexandros& Kumar, Rakesh& Chen, Deming. 2010. A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. International Journal of Reconfigurable Computing،Vol. 2010, no. 2010, pp.1-22.
https://search.emarefa.net/detail/BIM-454381
Modern Language Association (MLA)
Akram, Shoaib…[et al.]. A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. International Journal of Reconfigurable Computing No. 2010 (2010), pp.1-22.
https://search.emarefa.net/detail/BIM-454381
American Medical Association (AMA)
Akram, Shoaib& Papakonstantinou, Alexandros& Kumar, Rakesh& Chen, Deming. A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. International Journal of Reconfigurable Computing. 2010. Vol. 2010, no. 2010, pp.1-22.
https://search.emarefa.net/detail/BIM-454381
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-454381