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Pipeline FFT Architectures Optimized for FPGAs
Joint Authors
Peng, Yingning
Zhou, Bin
Hwang, David
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2009, Issue 2009 (31 Dec. 2009), pp.1-9, 9 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2009-09-14
Country of Publication
Egypt
No. of Pages
9
Main Subjects
Information Technology and Computer Science
Abstract EN
This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs.
Different optimization techniques and rounding schemes were explored.
The implementation results achieved better performance with lower resource usage than prior art.
The 16-bit 1024-point FFT with the R22SDF architecture had a maximum clock frequency of 95.2 MHz and used 2802 slices on the Spartan-3, a throughput per area ratio of 0.034 Msamples/s/slice.
The R4SDC architecture ran at 123.8 MHz and used 4409 slices on the Spartan-3, a throughput per area ratio of 0.028 Msamples/s/slice.
On Virtex-4, the 16-bit 1024-point R22SDF architecture ran at 235.6 MHz and used 2256 slice, giving a 0.104 Msamples/s/slice ratio; the 16-bit 1024-point R4SDC architecture ran at 219.2 MHz and used 3064 slices, giving a 0.072 Msamples/s/slice ratio.
The R22SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme.
This paper also shows that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors.
American Psychological Association (APA)
Zhou, Bin& Peng, Yingning& Hwang, David. 2009. Pipeline FFT Architectures Optimized for FPGAs. International Journal of Reconfigurable Computing،Vol. 2009, no. 2009, pp.1-9.
https://search.emarefa.net/detail/BIM-455563
Modern Language Association (MLA)
Zhou, Bin…[et al.]. Pipeline FFT Architectures Optimized for FPGAs. International Journal of Reconfigurable Computing No. 2009 (2009), pp.1-9.
https://search.emarefa.net/detail/BIM-455563
American Medical Association (AMA)
Zhou, Bin& Peng, Yingning& Hwang, David. Pipeline FFT Architectures Optimized for FPGAs. International Journal of Reconfigurable Computing. 2009. Vol. 2009, no. 2009, pp.1-9.
https://search.emarefa.net/detail/BIM-455563
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-455563