Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

Abstract EN

Embedded systems include an increasing share of analog/mixed-signal components that are tightly interwoven with functionality of digital HW/SW systems.

A challenge for verification is that even small deviations in analog components can lead to significant changes in system properties.

In this paper we propose the combination of range-based, semisymbolic simulation with assertion checking.

We show that this approach combines advantages, but as well some limitations, of multirun simulations with formal techniques.

The efficiency of the proposed method is demonstrated by several examples.