Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC

Abstract EN

The paper presents a unified hybrid architecture to compute the 8×8 integer inverse discrete cosine transform (IDCT) of multiple modern video codecs—AVS, H.264/AVC, VC-1, and HEVC (under development).

Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized “decompose and share” algorithm to compute the 8×8 IDCT.

The algorithm is later applied to four video standards.

The hardware-share approach ensures the maximum circuit reuse during the computation.

The architecture is designed with only adders and shifters to reduce the hardware cost significantly.

The design is implemented on FPGA and later synthesized in CMOS 0.18 um technology.

The results meet the requirements of advanced video coding applications.