![](/images/graphics-bg.png)
A Programmable Max-Log-MAP Turbo Decoder Implementation
Joint Authors
Takala, Jarmo Henrik
Salmela, Perttu
Sorokin, Harri
Source
Issue
Vol. 2008, Issue 2008 (31 Dec. 2008), pp.1-17, 17 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2008-12-22
Country of Publication
Egypt
No. of Pages
17
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations.
In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor.
The processor is accompanied with accelerating computing units, which can be controlled in detail.
With a novel memory interface, the dual-port memory for extrinsic information is avoided.
As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, which is comparable to pure hardware decoders.
With six turbo iterations and 277 MHz clock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology.
American Psychological Association (APA)
Salmela, Perttu& Sorokin, Harri& Takala, Jarmo Henrik. 2008. A Programmable Max-Log-MAP Turbo Decoder Implementation. VLSI Design،Vol. 2008, no. 2008, pp.1-17.
https://search.emarefa.net/detail/BIM-463145
Modern Language Association (MLA)
Salmela, Perttu…[et al.]. A Programmable Max-Log-MAP Turbo Decoder Implementation. VLSI Design No. 2008 (2008), pp.1-17.
https://search.emarefa.net/detail/BIM-463145
American Medical Association (AMA)
Salmela, Perttu& Sorokin, Harri& Takala, Jarmo Henrik. A Programmable Max-Log-MAP Turbo Decoder Implementation. VLSI Design. 2008. Vol. 2008, no. 2008, pp.1-17.
https://search.emarefa.net/detail/BIM-463145
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-463145