FPGA Fault Tolerant Arithmetic Logic : A Case Study Using Parallel-Prefix Adders
Joint Authors
Bollepalli, L. P. Deepthi
Hoe, David H. K.
Martinez, Chris D.
Source
Issue
Vol. 2013, Issue 2013 (31 Dec. 2013), pp.1-10, 10 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2013-11-07
Country of Publication
Egypt
No. of Pages
10
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation.
A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design.
The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs.
Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation.
A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference.
Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out.
The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain.
However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.
American Psychological Association (APA)
Hoe, David H. K.& Bollepalli, L. P. Deepthi& Martinez, Chris D.. 2013. FPGA Fault Tolerant Arithmetic Logic : A Case Study Using Parallel-Prefix Adders. VLSI Design،Vol. 2013, no. 2013, pp.1-10.
https://search.emarefa.net/detail/BIM-467699
Modern Language Association (MLA)
Hoe, David H. K.…[et al.]. FPGA Fault Tolerant Arithmetic Logic : A Case Study Using Parallel-Prefix Adders. VLSI Design No. 2013 (2013), pp.1-10.
https://search.emarefa.net/detail/BIM-467699
American Medical Association (AMA)
Hoe, David H. K.& Bollepalli, L. P. Deepthi& Martinez, Chris D.. FPGA Fault Tolerant Arithmetic Logic : A Case Study Using Parallel-Prefix Adders. VLSI Design. 2013. Vol. 2013, no. 2013, pp.1-10.
https://search.emarefa.net/detail/BIM-467699
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-467699