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An Efficient Multi-Core SIMD Implementation for H.264AVC Encoder
Joint Authors
Lambruschini, P.
Bariani, M.
Raggio, M.
Source
Issue
Vol. 2012, Issue 2012 (31 Dec. 2012), pp.1-14, 14 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2012-05-29
Country of Publication
Egypt
No. of Pages
14
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
The optimization process of a H.264/AVC encoder on three different architectures is presented.
The architectures are multi- and singlecore and SIMD instruction sets have different vector registers size.
The need of code optimization is fundamental when addressing HD resolutions with real-time constraints.
The encoder is subdivided in functional modules in order to better understand where the optimization is a key factor and to evaluate in details the performance improvement.
Common issues in both partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented for all the architectures.
Besides showing efficient video encoder implementations, one of the main purposes of this paper is to discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application performance.
Results about the achieved speedup are provided in order to compare the different implementations and evaluate the more suitable solutions for present and next generation video-coding algorithms.
American Psychological Association (APA)
Bariani, M.& Lambruschini, P.& Raggio, M.. 2012. An Efficient Multi-Core SIMD Implementation for H.264AVC Encoder. VLSI Design،Vol. 2012, no. 2012, pp.1-14.
https://search.emarefa.net/detail/BIM-470202
Modern Language Association (MLA)
Bariani, M.…[et al.]. An Efficient Multi-Core SIMD Implementation for H.264AVC Encoder. VLSI Design No. 2012 (2012), pp.1-14.
https://search.emarefa.net/detail/BIM-470202
American Medical Association (AMA)
Bariani, M.& Lambruschini, P.& Raggio, M.. An Efficient Multi-Core SIMD Implementation for H.264AVC Encoder. VLSI Design. 2012. Vol. 2012, no. 2012, pp.1-14.
https://search.emarefa.net/detail/BIM-470202
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-470202