Low-Cost Allocator Implementations for Networks-on-Chip Routers

Abstract EN

Cost-effective Networks-on-Chip (NoCs) routers are important for future SoCs and embedded devices.

Implementation results show that the generic virtual channel allocator (VA) and the generic switch allocator (SA) of a router consume large amount of area and power.

In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified.

Then, the deadlock problem for a combined switch and virtual channel allocator (SVA) is studied.

Next, the impact of the VA simplification on the router critical paths is analyzed.

Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA) are evaluated with a cycle-accurate network simulator and detailed VLSI implementations.

Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture.

Furthermore, cost savings are achieved without performance penalty.