A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos

Abstract EN

The motion estimation is the most complex module in a video encoder requiring a high processing throughput and high memory bandwidth, mainly when the focus is high-definition videos.

The throughput problem can be solved increasing the parallelism in the internal operations.

The external memory bandwidth may be reduced using a memory hierarchy.

This work presents a memory hierarchy model for a full-search motion estimation core.

The proposed memory hierarchy model is based on a data reuse scheme considering the full search algorithm features.

The proposed memory hierarchy expressively reduces the external memory bandwidth required for the motion estimation process, and it provides a very high data throughput for the ME core.

This throughput is necessary to achieve real time when processing high-definition videos.

When considering the worst bandwidth scenario, this memory hierarchy is able to reduce the external memory bandwidth in 578 times.

A case study for the proposed hierarchy, using 32×32 search window and 8×8 block size, was implemented and prototyped on a Virtex 4 FPGA.

The results show that it is possible to reach 38 frames per second when processing full HD frames (1920×1080 pixels) using nearly 299 Mbytes per second of external memory bandwidth.