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A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies
Joint Authors
Pandit, Soumya
Mandal, Chittaranjan
Patra, Amit
Source
Issue
Vol. 2011, Issue 2011 (31 Dec. 2011), pp.1-17, 17 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2011-09-15
Country of Publication
Egypt
No. of Pages
17
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
This paper presents a systematic methodology for the generation of high-level performance models for analog component blocks.
The transistor sizes of the circuit-level implementations of the component blocks along with a set of geometry constraints applied over them define the sample space.
A Halton sequence generator is used as a sampling algorithm.
Performance data are generated by simulating each sampled circuit configuration through SPICE.
Least squares support vector machine (LS-SVM) is used as a regression function.
Optimal values of the model hyper parameters are determined through a grid search-based technique and a genetic algorithm- (GA-) based technique.
The high-level models of the individual component blocks are combined analytically to construct the high-level model of a complete system.
The constructed performance models have been used to implement a GA-based high-level topology sizing process.
The advantages of the present methodology are that the constructed models are accurate with respect to real circuit-level simulation results, fast to evaluate, and have a good generalization ability.
In addition, the model construction time is low and the construction process does not require any detailed knowledge of circuit design.
The entire methodology has been demonstrated with a set of numerical results.
American Psychological Association (APA)
Pandit, Soumya& Mandal, Chittaranjan& Patra, Amit. 2011. A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. VLSI Design،Vol. 2011, no. 2011, pp.1-17.
https://search.emarefa.net/detail/BIM-474570
Modern Language Association (MLA)
Pandit, Soumya…[et al.]. A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. VLSI Design No. 2011 (2011), pp.1-17.
https://search.emarefa.net/detail/BIM-474570
American Medical Association (AMA)
Pandit, Soumya& Mandal, Chittaranjan& Patra, Amit. A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. VLSI Design. 2011. Vol. 2011, no. 2011, pp.1-17.
https://search.emarefa.net/detail/BIM-474570
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-474570