Shedding Physical Synthesis Area Bloat
Joint Authors
Zhou, Ying
Alpert, Charles J.
Trevillyan, Louise H.
Li, Zhuo
Sze, Cliff
Source
Issue
Vol. 2011, Issue 2011 (31 Dec. 2011), pp.1-10, 10 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2011-01-20
Country of Publication
Egypt
No. of Pages
10
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
Area bloat in physical synthesis not only increases power dissipation, but also creates congestion problems, forces designers to enlarge the die area, rerun the whole design flow, and postpone the design deadline.
As a result, it is vital for physical synthesis tools to achieve timing closure and low power consumption with intelligent area control.
The major sources of area increase in a typical physical synthesis flow are from buffer insertion and gate sizing, both of which have been discussed extensively in the last two decades, where the main focus is individual optimized algorithm.
However, building a practical physical synthesis flow with buffering and gate sizing to achieve the best timing/area/runtime is rarely discussed in any previous literatures.
In this paper, we present two simple yet efficient buffering and gate sizing techniques and achieve a physical synthesis flow with much smaller area bloat.
Compared to a traditional timing-driven flow, our work achieves 12% logic area growth reduction, 5.8% total area reduction, 10.1% wirelength reduction, and 770 ps worst slack improvement on average on 20 industrial designs in 65 nm and 45 nm.
American Psychological Association (APA)
Zhou, Ying& Alpert, Charles J.& Li, Zhuo& Sze, Cliff& Trevillyan, Louise H.. 2011. Shedding Physical Synthesis Area Bloat. VLSI Design،Vol. 2011, no. 2011, pp.1-10.
https://search.emarefa.net/detail/BIM-476753
Modern Language Association (MLA)
Zhou, Ying…[et al.]. Shedding Physical Synthesis Area Bloat. VLSI Design No. 2011 (2011), pp.1-10.
https://search.emarefa.net/detail/BIM-476753
American Medical Association (AMA)
Zhou, Ying& Alpert, Charles J.& Li, Zhuo& Sze, Cliff& Trevillyan, Louise H.. Shedding Physical Synthesis Area Bloat. VLSI Design. 2011. Vol. 2011, no. 2011, pp.1-10.
https://search.emarefa.net/detail/BIM-476753
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-476753