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Optimization Techniques for Verification of Out-of-Order Execution Machines
Author
Source
Journal of Electrical and Computer Engineering
Issue
Vol. 2010, Issue 2010 (31 Dec. 2010), pp.1-7, 7 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2010-09-08
Country of Publication
Egypt
No. of Pages
7
Main Subjects
Engineering Sciences and Information Technology
Information Technology and Computer Science
Abstract EN
We develop two optimization techniques, flush-machine and collapsed flushing, to improve the efficiency of automatic refinement-abased verification of out-of-order (ooo) processor models.
Refinement is a notion of equivalence that can be used to check that an ooo processor correctly implements all behaviors of its instruction set architecture (ISA), including deadlock detection.
The optimization techniques work by reducing the computational complexity of the refinement map, a function central to refinement proofs that maps ooo processor model states to ISA states.
This has a direct impact on the efficiency of verification, which is studied using 23 ooo processor models.
Flush-machine, is a novel optimization technique.
Collapsed flushing has been employed previously in the context of in-order processors.
We show how to apply collapsed flushing for ooo processor models.
Using both the optimizations together, we can handle 9 ooo models that could not be verified using standard flushing.
Also, the optimizations provided a speed up of 23.29 over standard flushing.
American Psychological Association (APA)
Srinivasan, Sudarshan K.. 2010. Optimization Techniques for Verification of Out-of-Order Execution Machines. Journal of Electrical and Computer Engineering،Vol. 2010, no. 2010, pp.1-7.
https://search.emarefa.net/detail/BIM-477762
Modern Language Association (MLA)
Srinivasan, Sudarshan K.. Optimization Techniques for Verification of Out-of-Order Execution Machines. Journal of Electrical and Computer Engineering No. 2010 (2010), pp.1-7.
https://search.emarefa.net/detail/BIM-477762
American Medical Association (AMA)
Srinivasan, Sudarshan K.. Optimization Techniques for Verification of Out-of-Order Execution Machines. Journal of Electrical and Computer Engineering. 2010. Vol. 2010, no. 2010, pp.1-7.
https://search.emarefa.net/detail/BIM-477762
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-477762