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Fine Control of Local Whitespace in Placement
Author
Source
Issue
Vol. 2008, Issue 2008 (31 Dec. 2008), pp.1-10, 10 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2008-09-23
Country of Publication
Egypt
No. of Pages
10
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as “whitespace.” This is done for a variety of reasons including the need for subsequent buffer insertion, as a means to ensure routability, signal integrity, and low coupling capacitance between wires, and to improve yield through DFM optimizations.
To this end, layout constraints often require a certain minimum fraction of whitespace in each region of the chip.
Our work introduces several techniques for allocation of whitespace in global, detail, and incremental placement.
Our experiments show how to efficiently improve wirelength by reallocating whitespace in legal placements at the large scale.
Additionally, for the first time in the literature, we empirically demonstrate high-precision control of whitespace in designs with macros and obstacles.
Our techniques consistently improve the quality of whitespace allocation of top-down as well as analytical placement methods and achieve low penalties on designs from the ISPD 2006 placement contest with minimal interconnect increase.
American Psychological Association (APA)
Roy, Jarrod A.. 2008. Fine Control of Local Whitespace in Placement. VLSI Design،Vol. 2008, no. 2008, pp.1-10.
https://search.emarefa.net/detail/BIM-478029
Modern Language Association (MLA)
Roy, Jarrod A.. Fine Control of Local Whitespace in Placement. VLSI Design No. 2008 (2008), pp.1-10.
https://search.emarefa.net/detail/BIM-478029
American Medical Association (AMA)
Roy, Jarrod A.. Fine Control of Local Whitespace in Placement. VLSI Design. 2008. Vol. 2008, no. 2008, pp.1-10.
https://search.emarefa.net/detail/BIM-478029
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-478029