Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits

Abstract EN

Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed.

These circuits use multiple-threshold MOS transistors for reducing power consumption.

The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters.

The performance of the proposed circuits is compared with the conventional MCML circuits.

The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones.

To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented.