Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (DFLL) Architecture
Joint Authors
Alser, Mohammed H.
Assaad, Maher
Source
Issue
Vol. 2012, Issue 2012 (31 Dec. 2012), pp.1-7, 7 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2012-09-18
Country of Publication
Egypt
No. of Pages
7
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
This paper presents a new architecture for a synchronized frequency multiplier circuit.
The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit.
Moreover, it can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip (SoC).
The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board.
The experimental results validate the expected phase tracking as well as the synthesizing properties.
For the measurement and validation purpose, an input reference signal in the range of 1.94–2.62 MHz was injected; the generated clock signal has a higher frequency, and it is in the range of 124.2–167.9 MHz with a frequency step (i.e., resolution) of 0.168 MHz.
The synthesized design requires 330 logic elements using the above Altera board.
American Psychological Association (APA)
Assaad, Maher& Alser, Mohammed H.. 2012. Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (DFLL) Architecture. VLSI Design،Vol. 2012, no. 2012, pp.1-7.
https://search.emarefa.net/detail/BIM-480351
Modern Language Association (MLA)
Assaad, Maher& Alser, Mohammed H.. Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (DFLL) Architecture. VLSI Design No. 2012 (2012), pp.1-7.
https://search.emarefa.net/detail/BIM-480351
American Medical Association (AMA)
Assaad, Maher& Alser, Mohammed H.. Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (DFLL) Architecture. VLSI Design. 2012. Vol. 2012, no. 2012, pp.1-7.
https://search.emarefa.net/detail/BIM-480351
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-480351