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Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain
Joint Authors
Jaquenod, Guillermo A.
Siman, Javier
Valls, Javier
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2014, Issue 2014 (31 Dec. 2014), pp.1-5, 5 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2014-01-09
Country of Publication
Egypt
No. of Pages
5
Main Subjects
Information Technology and Computer Science
Abstract EN
In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction.
For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs.
This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature) with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel.
American Psychological Association (APA)
Jaquenod, Guillermo A.& Valls, Javier& Siman, Javier. 2014. Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. International Journal of Reconfigurable Computing،Vol. 2014, no. 2014, pp.1-5.
https://search.emarefa.net/detail/BIM-480356
Modern Language Association (MLA)
Jaquenod, Guillermo A.…[et al.]. Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. International Journal of Reconfigurable Computing No. 2014 (2014), pp.1-5.
https://search.emarefa.net/detail/BIM-480356
American Medical Association (AMA)
Jaquenod, Guillermo A.& Valls, Javier& Siman, Javier. Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. International Journal of Reconfigurable Computing. 2014. Vol. 2014, no. 2014, pp.1-5.
https://search.emarefa.net/detail/BIM-480356
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-480356