A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Abstract EN

A processor design for singular value decomposition (SVD) and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems, is proposed and evaluated.

SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming.

An application specific instruction-set processor (ASIP) architecture is adopted to achieve flexibility in terms of operations and matrix size.

The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs) and arithmetic instructions specialized in complex matrix operations.