Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs
Joint Authors
Hosangadi, Anup
Kastner, Ryan
Mirzaei, Shahnam
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2010, Issue 2010 (31 Dec. 2010), pp.1-17, 17 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2010-03-29
Country of Publication
Egypt
No. of Pages
17
Main Subjects
Information Technology and Computer Science
Abstract EN
We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs).
Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations.
The first phase of our algorithm uses registered adders and hardwired shifts.
Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance.
The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design.
The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA).
We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method.
Also, there is 50% reduction in the total dynamic power consumption of the filters.
Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks.
For placement, there is a saving up to 20% in number of routing channels.
This results in lower congestion and up to 8% reduction in average wirelength.
American Psychological Association (APA)
Mirzaei, Shahnam& Kastner, Ryan& Hosangadi, Anup. 2010. Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs. International Journal of Reconfigurable Computing،Vol. 2010, no. 2010, pp.1-17.
https://search.emarefa.net/detail/BIM-491461
Modern Language Association (MLA)
Mirzaei, Shahnam…[et al.]. Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs. International Journal of Reconfigurable Computing No. 2010 (2010), pp.1-17.
https://search.emarefa.net/detail/BIM-491461
American Medical Association (AMA)
Mirzaei, Shahnam& Kastner, Ryan& Hosangadi, Anup. Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs. International Journal of Reconfigurable Computing. 2010. Vol. 2010, no. 2010, pp.1-17.
https://search.emarefa.net/detail/BIM-491461
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-491461