A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips

Abstract EN

Today's System-on-Chips (SoCs) design is extremely challenging because it involves complicated design tradeoffs and heterogeneous design expertise.

To explore the large solution space, system architects have to rely on system-level simulators to identify an optimized SoC architecture.

In this paper, we propose a system-level simulation framework, System Performance Simulation Implementation Mechanism, or SPSIM.

Based on SystemC TLM2.0, the framework consists of an executable SoC model, a simulation tool chain, and a modeling methodology.

Compared with the large body of existing research in this area, this work is aimed at delivering a high simulation throughput and, at the same time, guaranteeing a high accuracy on real industrial applications.

Integrating the leading TLM techniques, our simulator can attain a simulation speed that is not slower than that of the hardware execution by a factor of 35 on a set of real-world applications.

SPSIM incorporates effective timing models, which can achieve a high accuracy after hardware-based calibration.

Experimental results on a set of mobile applications proved that the difference between the simulated and measured results of timing performance is within 10%, which in the past can only be attained by cycle-accurate models.