Wave Pipelining Using Self Reset Logic
Joint Authors
Mourad, Samiha
Litvin, Miguel E.
Source
Issue
Vol. 2008, Issue 2008 (31 Dec. 2008), pp.1-6, 6 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2008-04-15
Country of Publication
Egypt
No. of Pages
6
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
This study presents a novel design approach combining wave pipelining and self reset logic, which provides an elegant solution at high-speed data throughput with significant savings in power and area as compared with other dynamic CMOS logic implementations.
To overcome some limitations in SRL art, we employ a new SRL family, namely, dual-rail self reset logic with input disable (DRSRL-ID).
These gates depict fairly constant timing parameters, specially the width of the output pulse, for varying fan-out and logic depth, helping accommodate process, supply voltage, and temperature variations (PVT).
These properties simplify the implementation of wave pipelined circuits.
General timing analysis is provided and compared with previous implementations.
Results of circuit implementation are presented together with conclusions and future work.
American Psychological Association (APA)
Litvin, Miguel E.& Mourad, Samiha. 2008. Wave Pipelining Using Self Reset Logic. VLSI Design،Vol. 2008, no. 2008, pp.1-6.
https://search.emarefa.net/detail/BIM-494815
Modern Language Association (MLA)
Litvin, Miguel E.& Mourad, Samiha. Wave Pipelining Using Self Reset Logic. VLSI Design No. 2008 (2008), pp.1-6.
https://search.emarefa.net/detail/BIM-494815
American Medical Association (AMA)
Litvin, Miguel E.& Mourad, Samiha. Wave Pipelining Using Self Reset Logic. VLSI Design. 2008. Vol. 2008, no. 2008, pp.1-6.
https://search.emarefa.net/detail/BIM-494815
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-494815