N Point DCT VLSI Architecture for Emerging HEVC Standard
Joint Authors
Rehman, Ata ur
Ahmed, Ashfaq
Shahid, Muhammad Usman
Source
Issue
Vol. 2012, Issue 2012 (31 Dec. 2012), pp.1-13, 13 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2012-08-08
Country of Publication
Egypt
No. of Pages
13
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
This work presents a flexible VLSI architecture to compute the N-point DCT.
Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations.
The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes.
The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications.
Finally, multiplications are completely eliminated using the lifting scheme.
The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.
American Psychological Association (APA)
Ahmed, Ashfaq& Shahid, Muhammad Usman& Rehman, Ata ur. 2012. N Point DCT VLSI Architecture for Emerging HEVC Standard. VLSI Design،Vol. 2012, no. 2012, pp.1-13.
https://search.emarefa.net/detail/BIM-495914
Modern Language Association (MLA)
Ahmed, Ashfaq…[et al.]. N Point DCT VLSI Architecture for Emerging HEVC Standard. VLSI Design No. 2012 (2012), pp.1-13.
https://search.emarefa.net/detail/BIM-495914
American Medical Association (AMA)
Ahmed, Ashfaq& Shahid, Muhammad Usman& Rehman, Ata ur. N Point DCT VLSI Architecture for Emerging HEVC Standard. VLSI Design. 2012. Vol. 2012, no. 2012, pp.1-13.
https://search.emarefa.net/detail/BIM-495914
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-495914