A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
Joint Authors
Source
Issue
Vol. 2013, Issue 2013 (31 Dec. 2013), pp.1-8, 8 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2013-01-08
Country of Publication
Egypt
No. of Pages
8
Main Subjects
Abstract EN
We present a compact and low-power rank-order searching (ROS) circuit that can be used for building associative memories and rank-order filters (ROFs) by employing time-domain computation and floating-gate MOS techniques.
The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones.
We aim to implement identification function as the first priority objective.
Filtering function would be implemented once the location identification function has been carried out.
The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology.
It consumes only 132.3 μW for an eight-input demonstration case.
American Psychological Association (APA)
Bui, Trong-Tu& Shibata, Tadashi. 2013. A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique. Journal of Engineering،Vol. 2013, no. 2013, pp.1-8.
https://search.emarefa.net/detail/BIM-496550
Modern Language Association (MLA)
Bui, Trong-Tu& Shibata, Tadashi. A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique. Journal of Engineering No. 2013 (2013), pp.1-8.
https://search.emarefa.net/detail/BIM-496550
American Medical Association (AMA)
Bui, Trong-Tu& Shibata, Tadashi. A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique. Journal of Engineering. 2013. Vol. 2013, no. 2013, pp.1-8.
https://search.emarefa.net/detail/BIM-496550
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-496550