A Novel Least Significant Bit First Processing Parallel CRC Circuit
Joint Authors
Qu, Xiujie
Yang, Zhanjie
Cao, Zhongkai
Source
Advances in Mechanical Engineering
Issue
Vol. 2013, Issue 2013 (31 Dec. 2013), pp.1-5, 5 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2013-12-22
Country of Publication
Egypt
No. of Pages
5
Main Subjects
Abstract EN
In HDLC serial communication protocol, CRC calculation can first process the most or least significant bit of data.
Nowadays most CRC calculation is based on the most significant bit (MSB) first processing.
An algorithm of the least significant bit (LSB) first processing parallel CRC is proposed in this paper.
Based on the general expression of the least significant bit first processing serial CRC, using state equation method of linear system, we derive a recursive formula by the mathematical deduction.
The recursive formula is applicable to any number of bits processed in parallel and any series of generator polynomial.
According to the formula, we present the parallel circuit of CRC calculation and implement it with VHDL on FPGA.
The results verify the accuracy and effectiveness of this method.
American Psychological Association (APA)
Qu, Xiujie& Cao, Zhongkai& Yang, Zhanjie. 2013. A Novel Least Significant Bit First Processing Parallel CRC Circuit. Advances in Mechanical Engineering،Vol. 2013, no. 2013, pp.1-5.
https://search.emarefa.net/detail/BIM-503988
Modern Language Association (MLA)
Qu, Xiujie…[et al.]. A Novel Least Significant Bit First Processing Parallel CRC Circuit. Advances in Mechanical Engineering No. 2013 (2013), pp.1-5.
https://search.emarefa.net/detail/BIM-503988
American Medical Association (AMA)
Qu, Xiujie& Cao, Zhongkai& Yang, Zhanjie. A Novel Least Significant Bit First Processing Parallel CRC Circuit. Advances in Mechanical Engineering. 2013. Vol. 2013, no. 2013, pp.1-5.
https://search.emarefa.net/detail/BIM-503988
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-503988
