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Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms
Joint Authors
Shanavas, I. Hameem
Gnanamurthy, Ramaswamy Kannan
Source
Issue
Vol. 2011, Issue 2011 (31 Dec. 2011), pp.1-9, 9 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2011-10-12
Country of Publication
Egypt
No. of Pages
9
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips.
The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning.
In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance.
In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue.
Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength.
The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth.
Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning.
MA applies some sort of local search for optimization of VLSI partitioning and floorplanning.
The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem.
MA can quickly produce optimal solutions for the popular benchmark.
American Psychological Association (APA)
Shanavas, I. Hameem& Gnanamurthy, Ramaswamy Kannan. 2011. Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms. VLSI Design،Vol. 2011, no. 2011, pp.1-9.
https://search.emarefa.net/detail/BIM-506255
Modern Language Association (MLA)
Shanavas, I. Hameem& Gnanamurthy, Ramaswamy Kannan. Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms. VLSI Design No. 2011 (2011), pp.1-9.
https://search.emarefa.net/detail/BIM-506255
American Medical Association (AMA)
Shanavas, I. Hameem& Gnanamurthy, Ramaswamy Kannan. Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms. VLSI Design. 2011. Vol. 2011, no. 2011, pp.1-9.
https://search.emarefa.net/detail/BIM-506255
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-506255