Reduced-Precision Redundancy on FPGAs
Joint Authors
Fuller, Megan
Wirthlin, Michael
Pratt, Brian
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2011, Issue 2011 (31 Dec. 2011), pp.1-12, 12 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2011-10-12
Country of Publication
Egypt
No. of Pages
12
Main Subjects
Information Technology and Computer Science
Abstract EN
Reduced-precision redundancy (RPR) has been shown to be a viable alternative to triple modular redundancy (TMR) for digital circuits.
This paper builds on previous research by offering a detailed analysis of the implementation of RPR on FPGAs to improve reliability in soft error environments.
Example implementations and fault injection experiments demonstrate the cost and benefits of RPR, showing how RPR can be used to improve the failure rate by up to 200 times over an unmitigated system at costs less than half that of TMR.
A novel method is also presented for improving the error-masking ability of RPR by up to 5 times at no additional hardware cost under certain conditions.
This research shows RPR to be a very flexible soft error mitigation technique and offers insight into its application on FPGAs.
American Psychological Association (APA)
Pratt, Brian& Fuller, Megan& Wirthlin, Michael. 2011. Reduced-Precision Redundancy on FPGAs. International Journal of Reconfigurable Computing،Vol. 2011, no. 2011, pp.1-12.
https://search.emarefa.net/detail/BIM-506361
Modern Language Association (MLA)
Pratt, Brian…[et al.]. Reduced-Precision Redundancy on FPGAs. International Journal of Reconfigurable Computing No. 2011 (2011), pp.1-12.
https://search.emarefa.net/detail/BIM-506361
American Medical Association (AMA)
Pratt, Brian& Fuller, Megan& Wirthlin, Michael. Reduced-Precision Redundancy on FPGAs. International Journal of Reconfigurable Computing. 2011. Vol. 2011, no. 2011, pp.1-12.
https://search.emarefa.net/detail/BIM-506361
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-506361
