Sub-threshold source -coupled logic (STSCL)‎ circuits for ultra low-power ring oscillators and logic circuits

Dissertant

al-Tawalibah, Nada Muhammad Mahmud

Thesis advisor

Hassan, Mahmud

Comitee Members

Muhaydat, Khaldun
Abu Gharbiyah, Khaldun
Mismar, Muhammad

University

Princess Sumaya University for Technology

Faculty

King Abdullah II Faculty of Engineering

Department

Department of Electrical Engineering

University Country

Jordan

Degree

Master

Degree Date

2015

English Abstract

Ultra-low power operations of electronic instruments are the need of the hour, due to the prompt growth of portable electronic systems.That means the ultra-low power consumption demands are very high in application fields, such as laptop computers, cellular phones and smart sensors.

In the modern integrated Circuits design, the power consumption is the major concern for achieving optimized performance.Sub-threshold region operation has acquired a very big importance for ultra-low power application requirements, when the supply voltages are scaled below the threshold voltage of the devices.

This work primarily focuses on the applicability of Sub-Threshold Source Coupled Logic (STSCL) for building digital circuits and systems with ability to work at extremely low voltages, promising to keep the required operation performance with significant power reduction.

In this work we use the STSCL technique to design and analyze important requisite circuits, inverter and the basic logic gates in 28nm technology.Also very low power Ring oscillator (RO) is implemented based on STSCL inverters.These basic gatescan be used to implement more complicated digital systems which wouldwork at low supply voltages and consume less power.

This thesis is inaugurated by presenting a theoretical analysis of the operation of the Source-coupled Logic (SCL) or MOS current-mode logic (MCML) circuits for implementing mixed-mode circuits, where, analog and digital design methodologies are applied in this work for efficient implementation of the STSCL gate and its biasing circuit called Replica bias circuit.

The replica bias circuit and its sub-parts like the operational amplifier play an important role in the STSCL circuits design, that provide the required biasing of controlling voltages for several of STSCL circuits and logic gates.

In this work the proposed operational amplifier was designed through 28nm technology using the gm/ID methodology which is the more efficient analog design method.

This method can efficiently applied in the modern nano technologies.

Also, this method helped us to select the required region of MOSFET operationefficiently.

On the other hand, we completed the STSCL circuits design based on a systematic design equations and calculations, where in this work, all the required process parameters were extracted successfully using a modified and adapted methods based on the design considerations.

The simulation results indicate the STSCL circuits features.

Therefore, the designed STSCL circuits have been operated and simulated for different low supply voltages, and at different temperatures to insure the high performance and to approve the ultra-low power consumption feature.

The proposed STSCL circuits: inverter, AND/NAND, OR/NOR and XOR/XNOR circuits have been simulated at -20o, 25o, 70o temperatures at 28nm technology, and the results show that the power consumption of these circuits is very low and ranged from 7pW (at -20o) to .5nW (at 70o), with time delay ranged from 1ns (at 70o) to 18ns (at -20o).This high performance of these basic STSCL gates can help to build more complicated digital systems with also high performance and very low power consumption.

In this work seven stages of the designed STSCL inverter have been used to build Ring Oscillator which is a very important part of most electronic systems and applications, The seven stage STSCL RO was operated with low voltage supply (0.4V) and low driven current (90pA).

The power consumption in the proposed STSCL ring oscillator is about 224.2nW which is very low compared to another logic style.

Main Subjects

Electronic engineering

No. of Pages

96

Table of Contents

• APA
• MLA
• AMA

Language

English

Data Type

Arab Theses

Record ID

BIM-693724