Cache coherence protocol design and simulation using IES (Invalid Exclusive read write Shared) state
Other Title(s)
تصميم و محاكاة بروتوكول الترابط في الذاكرة المخبئية باستخدام حالات (غير صالح، حصري في القراءة و الكتابة، مشترك)
Joint Authors
Jalil, Luma Fayiq
al-Rawi, Maha Abd al-Karim Hammud
al-Naqshabandi, Abir Diya
Source
Issue
Vol. 14, Issue 1 (31 Mar. 2017), pp.219-230, 12 p.
Publisher
University of Baghdad College of Science for Women
Publication Date
2017-03-31
Country of Publication
Iraq
No. of Pages
12
Main Subjects
Information Technology and Computer Science
Abstract EN
To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time.
In such systems, when installing different caches in different processors in shared memory architecture, the difficulties appear when there is a need to maintain consistency between the cache memories of different processors.
So, cache coherency protocol is very important in such kinds of system.
MSI, MESI, MOSI, MOESI, etc.
are the famous protocols to solve cache coherency problem.
We have proposed in this research integrating two states of MESI's cache coherence protocol which are Exclusive and Modified, which responds to a request from reading and writing at the same time and that are exclusive to these requests.
Also back to the main memory from one of the other processor that has a modified state is removed in using a proposed protocol when it is invalidated as a result of writing to that location that has the same address because in all cases it depends on the latest value written and if back to memory is used to protect data from loss; preprocessing steps to IES protocol is used to maintain and saving data in main memory when it evict from the cache.
All of this leads to increased processor efficiency by reducing access to main memory.
American Psychological Association (APA)
Jalil, Luma Fayiq& al-Rawi, Maha Abd al-Karim Hammud& al-Naqshabandi, Abir Diya. 2017. Cache coherence protocol design and simulation using IES (Invalid Exclusive read write Shared) state. Baghdad Science Journal،Vol. 14, no. 1, pp.219-230.
https://search.emarefa.net/detail/BIM-731445
Modern Language Association (MLA)
Jalil, Luma Fayiq…[et al.]. Cache coherence protocol design and simulation using IES (Invalid Exclusive read write Shared) state. Baghdad Science Journal Vol. 14, no. 1 (2017), pp.219-230.
https://search.emarefa.net/detail/BIM-731445
American Medical Association (AMA)
Jalil, Luma Fayiq& al-Rawi, Maha Abd al-Karim Hammud& al-Naqshabandi, Abir Diya. Cache coherence protocol design and simulation using IES (Invalid Exclusive read write Shared) state. Baghdad Science Journal. 2017. Vol. 14, no. 1, pp.219-230.
https://search.emarefa.net/detail/BIM-731445
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references : p. 229-230
Record ID
BIM-731445