Design principle and implementation of optical ternary adder and multiplier based on modified signed-digit number system

Other Title(s)

تصميم و تنفيذ الجامع و الضارب الثلاثي الضوئي بالاستناد إلى النظام العددي الرقمي المعدل ذي الإشارة

Dissertant

Thabit, Qabilah Qasim

Thesis advisor

al-Saffar, Ala A.

Comitee Members

Abd al-Rida, Haydar
Ali, Abd al-DhIm A.
Ali, Ramzi S.

University

University of Basrah

Faculty

Engineering College

Department

Department of Electrical Engineering

University Country

Iraq

Degree

Master

Degree Date

2012

English Abstract

Ternary optical computer (TOC) is one of the most important optical techniques due to its modern of emerging, ease of construct , and cheapness.

Therefore, the most reaschers made interesting and centered efforts toward it.

TOC is considered a new concept of optical computing that based on using a radix-2 signed-digit (SD) number system { 1 , 0, 1} which are encoded by horizontal polarized light, no-intensity light, and vertical polarized light, respectively.

This thesis, proposes a three new designs of processors, first is called traditional ternary optical processor (TTOP) which needs 22 BOUs/bit to perform addition operation.

Therefore, the design is capable of achieving three addition operations all their operands have length (1-14) bits, and the structure of TTOP adder consists of 4 sections, (vertical polarized- vertical polarized(VV), vertical polarized-horizontal polarized(V-H), horizontal polarizedhorizontal polarized(H-H), and horizontal polarized -vertical polarized(H-V)), while TTOP needs 4 BOUs/bits to perform multiplication operation.

Therefore, it is capable of achieving vector-matrix multiplication all their operands have length (2) bits, and the structure of TTOP multiplier consists of 3 sections (vertical polarized- vertical polarized(V-V), horizontal polarized- horizontal polarized(H-H), and horizontal polarized -vertical polarized(H-V)).

Second processor which is called modified ternary optical processor (MTOP); by using suitable control circuit to increase the length of word and to get higher speed than the above design; proposes the processor which needs 14 BOUs/bit to perform addition operation.

Therefore, it is capable of achieving three operations of addition all their operands have length (1-28) bits, and the structure of MTOP adder consists of 2 sections (vertical polarized- vertical polarized(V-V)), and horizontal polarized- horizontal polarized(H-H)), while MTOP needs 2 BOUs/bits to perform multiplication operation.

Therefore, it is capable of achieving vector-matrix multiplication all their operands have length (4) bits, and the structure of MTOP multiplier consists of 2 sections (vertical polarized-vertical polarized(V-V)), and horizontal polarized- horizontal polarized(H-H)).

Finally, the third processor which is called advanced ternary optical processor (ATOP) which needs 10 BOUs/bit to perform addition operation.

Therefore, it is capable of achieving three operations of addition all their operands have length (1- 42) bits, and the structure of ATOP adder consists of 2 sections (vertical polarized- vertical polarized(V-V)), and horizontal polarizedhorizontal polarized(H-H)), while multiplier the same as MTOP, each one of three designs achieves addition and multiplication operations, addition operation is implemented in two methods, conventional and pipeline methods (CM & PM), respectively.

While multiplication operation is implemented vectormatrix and then summation of PPs in CM.

Main Subjects

Electronic engineering

No. of Pages

120

Table of Contents

• APA
• MLA
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Language

English

Data Type

Arab Theses

Record ID

BIM-743284