Fast combined decimal binary multiplier based on redundant BCD 4221-8421digit recoding

Abstract EN

Many applications consider floating point arithmetic as a key component of the computations.

Combined decimal/binary arithmetic becomes an important topic supports high speed decimal/binary applications.

A new 64-bit (16×16 digit) combined decimal/binary multiplier is proposed and implemented in this work that can be used for both fused multiply add (FMA) and multiplier unit.

A new partial products reduction tree is shared between decimal and binary multiplier unit.

The valuation and comparison result between the proposed multiplier and the previous most recent works shows 4.66 % less delay than combined decimal/binary multiplier and 19.33 % less delay than fastest standalone decimal multiplier.

Index Terms- Multiplier, BCD 4-2-2-1, BCD 8-4-2-1, decimal, binary.