Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”

الملخص EN

This brief points out some problems when mapping the optimized GPCs using the heuristic of the paper above.

A thorough analysis revealed that a significant number of additional LUTs are required to route the signals when mapping the optimized designs on current FPGAs.

Taking these resources into account, the optimized GPCs require at least the same resources as previous state of the art.