Efficient Realization of BCD Multipliers Using FPGAs

الملخص EN

In this paper, a novel BCD multiplier approach is proposed.

The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns.

1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion.

The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products.

A binary-decimal compressor structure is developed and used for partial product reduction.

These reduced partial products are added in optimized 6-LUT BCD adders.

The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage.

The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction.

Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers.

Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.