![](/images/graphics-bg.png)
Efficient Realization of BCD Multipliers Using FPGAs
Joint Authors
Gao, Shuli
Langlois, J. M. Pierre
al-Khalili, Dhamin
Chabini, Noureddine
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2017, Issue 2017 (31 Dec. 2017), pp.1-12, 12 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2017-03-06
Country of Publication
Egypt
No. of Pages
12
Main Subjects
Information Technology and Computer Science
Abstract EN
In this paper, a novel BCD multiplier approach is proposed.
The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns.
1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion.
The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products.
A binary-decimal compressor structure is developed and used for partial product reduction.
These reduced partial products are added in optimized 6-LUT BCD adders.
The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage.
The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction.
Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers.
Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.
American Psychological Association (APA)
Gao, Shuli& al-Khalili, Dhamin& Langlois, J. M. Pierre& Chabini, Noureddine. 2017. Efficient Realization of BCD Multipliers Using FPGAs. International Journal of Reconfigurable Computing،Vol. 2017, no. 2017, pp.1-12.
https://search.emarefa.net/detail/BIM-1169411
Modern Language Association (MLA)
Gao, Shuli…[et al.]. Efficient Realization of BCD Multipliers Using FPGAs. International Journal of Reconfigurable Computing No. 2017 (2017), pp.1-12.
https://search.emarefa.net/detail/BIM-1169411
American Medical Association (AMA)
Gao, Shuli& al-Khalili, Dhamin& Langlois, J. M. Pierre& Chabini, Noureddine. Efficient Realization of BCD Multipliers Using FPGAs. International Journal of Reconfigurable Computing. 2017. Vol. 2017, no. 2017, pp.1-12.
https://search.emarefa.net/detail/BIM-1169411
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-1169411