Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

المؤلفون المشاركون

Duraisamy, V.
Shunbaga Pradeepa, T.
Somasundareswari, D.
Kishore Kumar, A.

المصدر

VLSI Design

العدد

المجلد 2013، العدد 2013 (31 ديسمبر/كانون الأول 2013)، ص ص. 1-9، 9ص.

الناشر

Hindawi Publishing Corporation

تاريخ النشر

2013-03-21

دولة النشر

مصر

عدد الصفحات

9

التخصصات الرئيسية

العلوم الهندسية و تكنولوجيا المعلومات

الملخص EN

Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits.

In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier.

Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply.

In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations.

To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced.

The power results of the proposed multiplier design are compared with the conventional CMOS implementation.

Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

نمط استشهاد جمعية علماء النفس الأمريكية (APA)

Kishore Kumar, A.& Somasundareswari, D.& Duraisamy, V.& Shunbaga Pradeepa, T.. 2013. Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL. VLSI Design،Vol. 2013, no. 2013, pp.1-9.
https://search.emarefa.net/detail/BIM-450417

نمط استشهاد الجمعية الأمريكية للغات الحديثة (MLA)

Kishore Kumar, A.…[et al.]. Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL. VLSI Design No. 2013 (2013), pp.1-9.
https://search.emarefa.net/detail/BIM-450417

نمط استشهاد الجمعية الطبية الأمريكية (AMA)

Kishore Kumar, A.& Somasundareswari, D.& Duraisamy, V.& Shunbaga Pradeepa, T.. Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL. VLSI Design. 2013. Vol. 2013, no. 2013, pp.1-9.
https://search.emarefa.net/detail/BIM-450417

نوع البيانات

مقالات

لغة النص

الإنجليزية

الملاحظات

Includes bibliographical references

رقم السجل

BIM-450417