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An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates
Joint Authors
Devi, T. Kalavathi
Palaniappan, Sakthivel
Source
Issue
Vol. 2015, Issue 2015 (31 Dec. 2015), pp.1-13, 13 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2015-10-07
Country of Publication
Egypt
No. of Pages
13
Main Subjects
Medicine
Information Technology and Computer Science
Abstract EN
Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems.
For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority.
This decoder meets the demand of high speed and low power.
At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined.
The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules.
The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB).
The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC).
The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.
American Psychological Association (APA)
Devi, T. Kalavathi& Palaniappan, Sakthivel. 2015. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates. The Scientific World Journal،Vol. 2015, no. 2015, pp.1-13.
https://search.emarefa.net/detail/BIM-1078934
Modern Language Association (MLA)
Devi, T. Kalavathi& Palaniappan, Sakthivel. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates. The Scientific World Journal No. 2015 (2015), pp.1-13.
https://search.emarefa.net/detail/BIM-1078934
American Medical Association (AMA)
Devi, T. Kalavathi& Palaniappan, Sakthivel. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates. The Scientific World Journal. 2015. Vol. 2015, no. 2015, pp.1-13.
https://search.emarefa.net/detail/BIM-1078934
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-1078934