An optimized multiplierless hardware design of fast 2-D DCT IDCT for image video coding

Abstract EN

The Two-Dimensional Discrete Cosine Transform / Inverse Discrete Cosine Transform (2-D DCT/IDCT) is a key algorithm in image and video coding applications.

Therefore, the optimization of its hardware implementation requires low complexity design.

For this purpose, a possible solution is to avoid multiplications and to replace them by additions and shifts, while meeting the requirement of real time applications.

In this paper, an optimized design for a multiplierless hardware implementation of fast 2-D DCT/IDCT based on modified Loeffler algorithm is achieved, in which a new approach is used to reduce the amount of additions and shift operators.

This approach is based on the combination of three representations of constant coefficient multiplications: natural binary, canonic signed digit (CSD) and a new signed digit representation.

The optimized 1-D DCT/IDCT design is developed, by selecting for each constant coefficient multiplication the suitable representation method that allows simultaneously a maximum frequency operation and a minimum number of additions and shift operators.

The hardware implementation of 2-D DCT/IDCT is performed with the optimized 1-D DCT/IDCT design and a robust transpose buffer.

All these pipelined hardware implementations are described in VHDL hardware language, synthesized and implemented on low cost FPGA.

This proposed 2-D DCT/IDCT design reduces the computational complexity compared to other previous designs.

The implementation results of the proposed 2-D DCT/IDCT show an increase of the maximum frequency by 14% and a decrease of resources usage by 18.5% in comparison with previous design based on modified Loeffler algorithm.