FPGA implementation of an array processor

Abstract EN

This paper describes how to map the array processor to the Xilinx Field Programmable Gate Array (FPGA) Chip.

The design- is connected to personal computer and tested as a matrix multiplication using a high level (Visual Basic) program.

'the developed con^’olution architecture was capturcd through the use of the very High Scale Hardware Description Language (VHDL).

Xilinx Foundation series (4.

1i) Computer Aided Design (CAD) software package was used to synthesize and implement the architecture of the array processor to the FPGA chip.

Before the 2rchitecture was prototyped into the prototyping board for experimental testing, the architecture was functionally and performance validated through Hardware Description language (HDL) software simulation via post-synthesis and post-impiementation software simulations.