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Delay Efficient 32-Bit Carry-Skip Adder
Joint Authors
Radhakrishnan, Damu
Lin, Yu Shen
Source
Issue
Vol. 2008, Issue 2008 (31 Dec. 2008), pp.1-8, 8 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2008-04-02
Country of Publication
Egypt
No. of Pages
8
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper.
A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders.
The group generate and group propagate functions are generated in parallel with the carry generation for each block.
The optimum block sizes are decided by considering the critical path into account.
The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders.
The adder is implemented in 0.25 μm CMOS technology at 3.3 V.
The critical delay for the proposed adder is 3.4 nanoseconds.
The simulation results show that the proposed adder is 18% faster than the current fastest carry-skip adder.
American Psychological Association (APA)
Lin, Yu Shen& Radhakrishnan, Damu. 2008. Delay Efficient 32-Bit Carry-Skip Adder. VLSI Design،Vol. 2008, no. 2008, pp.1-8.
https://search.emarefa.net/detail/BIM-455513
Modern Language Association (MLA)
Lin, Yu Shen& Radhakrishnan, Damu. Delay Efficient 32-Bit Carry-Skip Adder. VLSI Design No. 2008 (2008), pp.1-8.
https://search.emarefa.net/detail/BIM-455513
American Medical Association (AMA)
Lin, Yu Shen& Radhakrishnan, Damu. Delay Efficient 32-Bit Carry-Skip Adder. VLSI Design. 2008. Vol. 2008, no. 2008, pp.1-8.
https://search.emarefa.net/detail/BIM-455513
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-455513