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Semidigital PLL Design for Low-Cost Low-Power Clock Generation
Joint Authors
Rhee, Woogeun
Wang, Zhihua
Xu, Ni
Source
Journal of Electrical and Computer Engineering
Issue
Vol. 2011, Issue 2011 (31 Dec. 2011), pp.1-9, 9 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2011-12-06
Country of Publication
Egypt
No. of Pages
9
Main Subjects
Engineering Sciences and Information Technology
Information Technology and Computer Science
Abstract EN
This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation.
With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature.
Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.
American Psychological Association (APA)
Xu, Ni& Rhee, Woogeun& Wang, Zhihua. 2011. Semidigital PLL Design for Low-Cost Low-Power Clock Generation. Journal of Electrical and Computer Engineering،Vol. 2011, no. 2011, pp.1-9.
https://search.emarefa.net/detail/BIM-456098
Modern Language Association (MLA)
Xu, Ni…[et al.]. Semidigital PLL Design for Low-Cost Low-Power Clock Generation. Journal of Electrical and Computer Engineering No. 2011 (2011), pp.1-9.
https://search.emarefa.net/detail/BIM-456098
American Medical Association (AMA)
Xu, Ni& Rhee, Woogeun& Wang, Zhihua. Semidigital PLL Design for Low-Cost Low-Power Clock Generation. Journal of Electrical and Computer Engineering. 2011. Vol. 2011, no. 2011, pp.1-9.
https://search.emarefa.net/detail/BIM-456098
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-456098