9T Full Adder Design in Subthreshold Region

Abstract EN

This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications.

The proposed circuit consists of a new logic which is used to implement Sum module.

The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders.

Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications.

All simulations are performed on 45 nm standard model on Tanner EDA tool version 13.0.