Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits
Joint Authors
Bahrebar, Poona
Nikoubin, Tooraj
Pouri, Sara
Navi, Keivan
Iravani, Vaez
Source
Issue
Vol. 2010, Issue 2010 (31 Dec. 2010), pp.1-17, 17 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2010-04-27
Country of Publication
Egypt
No. of Pages
17
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
A new transistor sizing algorithm, SEA (Simple Exact Algorithm), for optimizing low-power and high-speed arithmetic integrated circuits is proposed.
In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP), chip area or the combination of them are considered as the advantages of this new algorithm.
More exhaustive rules of grouping transistors are the main trait of our algorithm.
Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability.
According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively.
By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved.
All the simulations have been performed with 0.13 μm technology based on the BSIM3v3 model using HSpice simulator software.
American Psychological Association (APA)
Nikoubin, Tooraj& Bahrebar, Poona& Pouri, Sara& Navi, Keivan& Iravani, Vaez. 2010. Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits. VLSI Design،Vol. 2010, no. 2010, pp.1-17.
https://search.emarefa.net/detail/BIM-458646
Modern Language Association (MLA)
Nikoubin, Tooraj…[et al.]. Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits. VLSI Design No. 2010 (2010), pp.1-17.
https://search.emarefa.net/detail/BIM-458646
American Medical Association (AMA)
Nikoubin, Tooraj& Bahrebar, Poona& Pouri, Sara& Navi, Keivan& Iravani, Vaez. Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits. VLSI Design. 2010. Vol. 2010, no. 2010, pp.1-17.
https://search.emarefa.net/detail/BIM-458646
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-458646