Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
Joint Authors
Molavi, Reza
Djahanshahi, Hormoz
Mirabbasi, Shahriar
Zavari, Rod
Source
Journal of Electrical and Computer Engineering
Issue
Vol. 2013, Issue 2013 (31 Dec. 2013), pp.1-8, 8 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2013-07-29
Country of Publication
Egypt
No. of Pages
8
Main Subjects
Engineering Sciences and Information Technology
Information Technology and Computer Science
Abstract EN
Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications.
However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance.
This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner.
Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8 GHz is designed and implemented in a 65 nm digital CMOS process.
Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device.
American Psychological Association (APA)
Molavi, Reza& Djahanshahi, Hormoz& Zavari, Rod& Mirabbasi, Shahriar. 2013. Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration. Journal of Electrical and Computer Engineering،Vol. 2013, no. 2013, pp.1-8.
https://search.emarefa.net/detail/BIM-466204
Modern Language Association (MLA)
Molavi, Reza…[et al.]. Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration. Journal of Electrical and Computer Engineering No. 2013 (2013), pp.1-8.
https://search.emarefa.net/detail/BIM-466204
American Medical Association (AMA)
Molavi, Reza& Djahanshahi, Hormoz& Zavari, Rod& Mirabbasi, Shahriar. Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration. Journal of Electrical and Computer Engineering. 2013. Vol. 2013, no. 2013, pp.1-8.
https://search.emarefa.net/detail/BIM-466204
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-466204