A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators
Joint Authors
Source
Issue
Vol. 2008, Issue 2008 (31 Dec. 2008), pp.1-8, 8 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2008-09-24
Country of Publication
Egypt
No. of Pages
8
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper.
Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively.
By using separate regulators, the area and the power consumption of the regulator can be reduced.
Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise.
The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process.
The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added.
By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled.
American Psychological Association (APA)
Lee, Tzung-Je& Wang, Chua-Chin. 2008. A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. VLSI Design،Vol. 2008, no. 2008, pp.1-8.
https://search.emarefa.net/detail/BIM-477559
Modern Language Association (MLA)
Lee, Tzung-Je& Wang, Chua-Chin. A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. VLSI Design No. 2008 (2008), pp.1-8.
https://search.emarefa.net/detail/BIM-477559
American Medical Association (AMA)
Lee, Tzung-Je& Wang, Chua-Chin. A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. VLSI Design. 2008. Vol. 2008, no. 2008, pp.1-8.
https://search.emarefa.net/detail/BIM-477559
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-477559