A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands
Joint Authors
Kamakoti, V.
Benini, Luca
Murali, Srinivasan
Kumar, M. Pawan
Kumar, Anish S.
De Micheli, Giovanni
Source
Journal of Electrical and Computer Engineering
Issue
Vol. 2012, Issue 2012 (31 Dec. 2012), pp.1-12, 12 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2012-02-28
Country of Publication
Egypt
No. of Pages
12
Main Subjects
Engineering Sciences and Information Technology
Information Technology and Computer Science
Abstract EN
Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem.
Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity.
Also, congestion effects that occur during network operation need to be captured when sizing the buffers.
Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters.
To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands.
Our algorithm considers both the static and dynamic effects when sizing buffers.
We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth.
Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.
American Psychological Association (APA)
Kumar, Anish S.& Kumar, M. Pawan& Murali, Srinivasan& Kamakoti, V.& Benini, Luca& De Micheli, Giovanni. 2012. A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. Journal of Electrical and Computer Engineering،Vol. 2012, no. 2012, pp.1-12.
https://search.emarefa.net/detail/BIM-479601
Modern Language Association (MLA)
Kumar, Anish S.…[et al.]. A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. Journal of Electrical and Computer Engineering No. 2012 (2012), pp.1-12.
https://search.emarefa.net/detail/BIM-479601
American Medical Association (AMA)
Kumar, Anish S.& Kumar, M. Pawan& Murali, Srinivasan& Kamakoti, V.& Benini, Luca& De Micheli, Giovanni. A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. Journal of Electrical and Computer Engineering. 2012. Vol. 2012, no. 2012, pp.1-12.
https://search.emarefa.net/detail/BIM-479601
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-479601