Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Abstract EN

A novel concept of logic redundancy insertion is presented that facilitates significant latency reduction in self-timed adder circuits.

The proposed concept is universal in the sense that it can be extended to a variety of self-timed design methods.

Redundant logic can be incorporated to generate efficient self-timed realizations of iterative logic specifications.

Based on the case study of a 32-bit self-timed carry-ripple adder, it has been found that redundant implementations minimize the data path latency by 21.1% at the expense of increases in area and power by 2.3% and 0.8% on average compared to their nonredundant counterparts.

However, when considering further peephole logic optimizations, it has been observed in a specific scenario that the delay reduction could be as high as 31% while accompanied by only meager area and power penalties of 0.6% and 1.2%, respectively.

Moreover, redundant logic adders pave the way for spacer propagation in constant time and garner actual case latency for addition of valid data.