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Static Switching Dynamic Buffer Circuit
Joint Authors
Mishra, R. A.
Nagaria, Rajendra Kumar
Pandey, A. K.
Source
Issue
Vol. 2013, Issue 2013 (31 Dec. 2013), pp.1-11, 11 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2013-03-26
Country of Publication
Egypt
No. of Pages
11
Main Subjects
Abstract EN
We proposed footless domino logic buffer circuit.
It minimizes redundant switching at the dynamic and the output nodes.
The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption.
Simulation is done using 0.18 µm CMOS technology.
We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply.
Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.
American Psychological Association (APA)
Pandey, A. K.& Mishra, R. A.& Nagaria, Rajendra Kumar. 2013. Static Switching Dynamic Buffer Circuit. Journal of Engineering،Vol. 2013, no. 2013, pp.1-11.
https://search.emarefa.net/detail/BIM-487846
Modern Language Association (MLA)
Pandey, A. K.…[et al.]. Static Switching Dynamic Buffer Circuit. Journal of Engineering No. 2013 (2013), pp.1-11.
https://search.emarefa.net/detail/BIM-487846
American Medical Association (AMA)
Pandey, A. K.& Mishra, R. A.& Nagaria, Rajendra Kumar. Static Switching Dynamic Buffer Circuit. Journal of Engineering. 2013. Vol. 2013, no. 2013, pp.1-11.
https://search.emarefa.net/detail/BIM-487846
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-487846