High-Performance Timing-Driven Rank Filter
Joint Authors
Szántó, Péter
Szedő, Gábor
Fehér, Béla
Source
Issue
Vol. 2008, Issue 2008 (31 Dec. 2008), pp.1-6, 6 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2008-01-31
Country of Publication
Egypt
No. of Pages
6
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
This paper presents an FPGA implementation of a high-performance rank filter for video and image processing.
The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance.
By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.
American Psychological Association (APA)
Szántó, Péter& Szedő, Gábor& Fehér, Béla. 2008. High-Performance Timing-Driven Rank Filter. VLSI Design،Vol. 2008, no. 2008, pp.1-6.
https://search.emarefa.net/detail/BIM-496015
Modern Language Association (MLA)
Szántó, Péter…[et al.]. High-Performance Timing-Driven Rank Filter. VLSI Design No. 2008 (2008), pp.1-6.
https://search.emarefa.net/detail/BIM-496015
American Medical Association (AMA)
Szántó, Péter& Szedő, Gábor& Fehér, Béla. High-Performance Timing-Driven Rank Filter. VLSI Design. 2008. Vol. 2008, no. 2008, pp.1-6.
https://search.emarefa.net/detail/BIM-496015
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-496015
