An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H
Joint Authors
Carvajal, Wilmar
Van Noije, Wilhelmus
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2012, Issue 2012 (31 Dec. 2012), pp.1-17, 17 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2012-08-16
Country of Publication
Egypt
No. of Pages
17
Main Subjects
Information Technology and Computer Science
Abstract EN
This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design.
The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology.
Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design.
Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12 mW while sampling a 500 kHz input signal.
Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 μm AMS technology, and some postlayout results are shown.
American Psychological Association (APA)
Carvajal, Wilmar& Van Noije, Wilhelmus. 2012. An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H. International Journal of Reconfigurable Computing،Vol. 2012, no. 2012, pp.1-17.
https://search.emarefa.net/detail/BIM-497984
Modern Language Association (MLA)
Carvajal, Wilmar& Van Noije, Wilhelmus. An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H. International Journal of Reconfigurable Computing No. 2012 (2012), pp.1-17.
https://search.emarefa.net/detail/BIM-497984
American Medical Association (AMA)
Carvajal, Wilmar& Van Noije, Wilhelmus. An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H. International Journal of Reconfigurable Computing. 2012. Vol. 2012, no. 2012, pp.1-17.
https://search.emarefa.net/detail/BIM-497984
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-497984