Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC : A Survey
Joint Authors
Devashrayee, Niranjan
Dasgupta, Kankar S.
Mehta, Usha S.
Source
Issue
Vol. 2011, Issue 2011 (31 Dec. 2011), pp.1-7, 7 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2011-01-19
Country of Publication
Egypt
No. of Pages
7
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
Test power is the major issue for current generation VLSI testing.
It has become the biggest concern for today's SoC.
While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue.
It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques.
To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented.
The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power.
Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.
American Psychological Association (APA)
Mehta, Usha S.& Dasgupta, Kankar S.& Devashrayee, Niranjan. 2011. Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC : A Survey. VLSI Design،Vol. 2011, no. 2011, pp.1-7.
https://search.emarefa.net/detail/BIM-510617
Modern Language Association (MLA)
Mehta, Usha S.…[et al.]. Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC : A Survey. VLSI Design No. 2011 (2011), pp.1-7.
https://search.emarefa.net/detail/BIM-510617
American Medical Association (AMA)
Mehta, Usha S.& Dasgupta, Kankar S.& Devashrayee, Niranjan. Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC : A Survey. VLSI Design. 2011. Vol. 2011, no. 2011, pp.1-7.
https://search.emarefa.net/detail/BIM-510617
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-510617